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freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor application note AN2635 rev. 4, 10/2005 on-chip flash programming routines for mc68hc908lb8, mc68hc908ql4, mc68hc908qb8, mc68hc908qb4, mc68hc908qy8, and mc68hc908qy4a series 1 by: kazue kikuchi mcu applications engineering austin, texas introduction this application note applies to the mc68hc908lb8, mc68hc908ql4, mc68hc908qb4/qb8/qy8, and mc68hc908qy4a series 1 flash-based microcontroller units (mcus). to program, erase, and verify flash, these mcus have on-chip flash support routines residing in rom (read-only memory). these routines may be accessed in either user mode or monitor mode and eliminate the need to develop separate flash routines for applications. this application note describes how to call each of the routines in user software, what is performed, and what is returned as confirmation of routine execution. the software files are available as a zip file, AN2635sw, from the freescale semiconductor website: www.freescale.com note with the exception of mask set errata documents, if any other freescale semiconductor document contains information that conflicts with the information in the device data sheet, the data sheet should be considered to have the most current and correct data. 1. mc68hc908qy4a series includes mc68hc908 qy4a , mc68hc908 qy2a , mc68hc908 qy1a , mc68hc908 qt4a , mc68hc908 qt2a , mc68hc908 qt1a
on-chip flash programming routines, rev. 4 2 freescale semiconductor routines supported in rom flash overview the flash cell used on these 0.5- mcus is an industry-proven split-gate cell. the cell uses channel hot electron injection for programming and fowler-nordheim tunnelling for erasing. all programming voltages are generated internally by a charge pump from a single connection to v dd . with the quick byte-programming time and the organization of the flash array into 32-byte rows, the entire 8-kbyte memory can be programmed in less than one-half second. this type of flash is specified to withstand at least 10,000 program/erase cycles and has enhanced reliability over previous technology. usually, split-gate flash is programmed on a row basis and erased on a page basis. also, an entire specified array can be mass erased. for the target mcus, rows are 32 bytes and pages are 64 bytes (two rows of 32 bytes each). routines supported in rom in the rom, six routines are supported. because the rom has a jump table, the user does not call the routines with direct addresses. therefore, the calling addresses will not change?ven when the rom code is updated in the future. this section introduces each routine briefly. details are discussed in later sections. getbyte this routine is used to receive a byte serially on the general-purpose i/o pta0. the receiving baud rate is the same as the baud rate used in monitor mode. in the getbyte routine, the getbit routine is called to generate baud rates required for each mcu. putbyte this routine is used to send a byte serially on the general-purpose i/o pta0. the sending baud rate is the same as the baud rate specified in monitor mode. rdvrrng this routine is used to perform one of two options. using the send-out option, this routine reads flash locations and sends the data out serially on the general-purpose i/o pta0. using to verify option, this routine verifies the flash data against data in a specific ram location, which is referred to as a data array. prgrnge this routine is used to program a contiguous range of flash locations that is up to 32 bytes and in the same row. programming data is first loaded into the data array. prgrnge can be used when the internal operating frequency (f op ) is between 1.0 mhz and 8.4 mhz.
variables used in the routines on-chip flash programming routines, rev. 4 freescale semiconductor 3 erarnge this routine is used to erase either a page (64 bytes) or the whole array of flash. it can be used when the internal operating frequency (f op ) is between 1.0 mhz and 8.4 mhz. delnus this routine can generate a specified delay based on the values of register x and accumulator (a) as parameters. delnus is used in erarnge routine. variables used in the routines the rdvrnge, prgrnge, and erarnge routines require certain registers and/or ram locations to be initialized before calling the routines in the user software. table 1 shows variables used in the routines and their locations. ram in general, ram in table 1 indicates the ram start address. see table 2 for ram start locations for specific mcus. for example, the ram start address for the mc68hc908lb8 (and each mcu currently in the table) is $80. ctrlbyt the control byte (ctrlbyt) is located at ram address ram+$8 and is used for the erarnge routine. in the case of the mc68hc908lb8, the ctrlbyt is located at $88. bit 6 in this location is used to specify either mass (1) or page (0) erase. the other bits must be 0. if one or more of these bits (except bit 6) is initialized with 1, the erase operation is not executed. table 1. variables and their locations location variable name size (bytes) description ram ?ram+7 reserved 8 reserved for future use ram+$8 ctrlbyt 1 control byte setting erase size ram+$9 cpuspd 1 cpu speed ?the nearest integer of f op (in mhz) 4; for example, if f op = 2.4576 mhz, cpuspd = 10 ram+$a, ram+$b laddr 2 last address of a 16-bit range ram+$c data varies first location of data array; data array size must match a programming or verifying range registers h:x 2 beginning address of a 16-bit range
on-chip flash programming routines, rev. 4 4 freescale semiconductor how to use the routines cpuspd to set up proper delays used in the prgrnge and erarnge routines, a value indicating the internal operating frequency (f op ) must be stored at cpuspd, which is located at ram address ram+$9. in the case of the mc68hc908lb8, the cpuspd is located at $89. the cpuspd value is the nearest integer of f op (in mhz) times 4. for example, if f op is 4.2 mhz, the cpuspd value is 17. if f op is 2.1 mhz, the cpuspd value is 8. setting a correct cpuspd value is very important to program or erase the flash successfully. laddr a range specifies the flash locations to be read, verified, or programmed. the 16-bit value in ram addresses ram+$a and ram+$b holds the last address of a range. the addresses ram+$a and ram+$b are the high and low bytes of the last address, respectively. in the case of mc68hc908lb8, the laddr is located at $8a and $8b. laddr is used for rdvrrng and prgrnge routines. data data is the first location of the data array and is located at ram address ram+$c. for the mc68hc908lb8, the data is located at $8c. the array is used for loading program or verify data. the data array must be in the zero page and its size must match the size of the range to be programmed or verified. registers h:x in the rdvrrng and prgrnge routines, registers h and x are initialized with a 16-bit value representing the first address of a range. high and low bytes of the address are stored to registers h and x, respectively. in the erarnge routine, registers h and x are initialized with an address which is within the page or entire array to be erased. how to use the routines this section describes the details of each routine. table 2 provides necessary addresses used in the on-chip flash routines for each mcu type. table 3 summarizes the six routines. table 2. mcu type vs. necessary addresses required for on-chip flash routines mcu name ram getbyte putbyte rdvrrng prgrnge erarnge delnus mc68hc908 lb8 $80 $037e $0381 $0384 $038a $0387 $038d mc68hc908 ql4 $80 $2b7e $2b81 $2b84 $2b8a $2b87 $2b8d mc68hc908 qy4a series (1) notes: 1. mc68hc908qy4a series includes mc68hc908 qy4a , mc68hc908 qy2a , mc68hc908 qy1a , mc68hc908 qt4a , mc68hc908 qt2a , mc68hc908 qt1a $80 $2800 $280f $2803 $2809 $2806 $280c mc68hc908 qb4/qb8, mc68hc908 qy8 $80 $2800 $280f $2803 $2809 $2806 $280c
how to use the routines on-chip flash programming routines, rev. 4 freescale semiconductor 5 table 3. summary of on-chip flash support routines getbyte putbyte rdvrrng prgrnge erarnge delnus routine description get a data byte serially through pta0 send a data byte serially through pta0 read and/or verify a flash range program a flash range (maximum 32 bytes in a row) erase a page or entire array generate delay 3 a x + 8 (cycles) internal operating frequency ( f op ) 1 mhz to 8.4 mhz 1 mhz to 8.4 mhz hardware requirement pullup on pta0 pullup on pta0 for send-out option, pullup on pta0 n/a n/a n/a entry conditions pta0: input (ddra0 = 0) pta0: input and 0 data bit (ddra0 = 0, pta0 = 0) a: data to be sent h:x: first address of range laddr: last address of range a: a = $00 for send-out option or a $00 for verify option for send-out option pta0: input and 0 data bit (ddra0 = 0, pta0 = 0) for verify option, data array: load data to be veri?d against flash read data h:x: first address of range laddr: last address of range cpuspd: the nearest integer f op (in mhz) times 4 data array: load data to be programmed h:x: address within a page or an array to be erased cpuspd: the nearest integer f op (in mhz) times 4 ctrlbyt: $40 = mass erase $00 = page erase a: value between 4 and 255 x: value between 1 and 255
on-chip flash programming routines, rev. 4 6 freescale semiconductor how to use the routines exit conditions a: data received through pta0 c-bit: framing error indicator (error: c = 0) a, x: no change pta0: input and 0 data bit (ddra0 = 0, pta0 = 0) a: checksum h:x: next flash address c-bit: verify result indicator (success: c = 1) data array: data replaced with flash read data (verify option) h:x: next flash address h:x: no change i bit i bit is set i bit is set cop not serviced not serviced serviced serviced serviced not serviced subroutines called getbit putbyte for send-out option delnus ram variable laddr (2 bytes), data array (no size limitation as long as in the zero page) cpuspd, laddr (2 bytes), data array (maximum 32 bytes) ctrlbyt, cpuspd stack used (including theroutine? call) 6 bytes 4 bytes 9 bytes for verify option 11 bytes for send-out option 9 bytes 7 bytes 3 bytes table 3. summary of on-chip flash support routines (continued) getbyte putbyte rdvrrng prgrnge erarnge delnus
how to use the routines on-chip flash programming routines, rev. 4 freescale semiconductor 7 getbyte getbyte is a routine that receives a byte on the general-purpose i/o pta0, and the received value is returned to the calling routine in the accumulator (a). this routine is also used in monitor mode so that it expects the same non-return-to-zero (nrz) communication protocol and baud rates. this routine detects a framing error when a stop bit is not detected. if the carry (c) bit of the condition control register (ccr) is cleared after returning from this routine, a framing error occurred during the data receiving process. therefore, the data in a is not reliable. the user software is responsible for handling such errors. interrupts are not masked (the i bit is not set) and the cop is not serviced in the getbyte routine. user software should ensure that interrupts are blocked during character reception. to provide a specific communication baud rate, getbyte calls the getbit subroutine. in the getbyte routine, two different clock sources, internal clock and external clock, are supported. for example, the mc68hc908lb8 usually has a trimmed internal bus clock of 4 mhz and an external bus clock of 2.4576 mhz. for the mcu to distinguish which clock source is currently selected, the ecgst (external clock generator status) bit in the oscstat (oscillator status register) is monitored in the getbit subroutine. when ecgst bit is set, the external clock is selected as a clock source. when the bit is cleared, the internal clock is selected. the baud rate is defined by f op divided by a constant value, which is specified in the development support section in the device data sheet. in the case of the mc68hc908lb8, the baud rate of an internal clock source is defined by f op divided by 417. if the internal bus clock is 4 mhz, the baud rate is 4 mhz/417 = 9592. therefore, the closest pc baud rate is 9600. on the other hand, the baud rate of an external clock source is f op divided by 256. when an external bus clock is 2.4576 mhz, the baud rate is 2.4576 mhz/256 = 9600. to use this routine, some hardware setup is required. the general-purpose i/o pta0 must be pulled up. for more information, refer to the development support section in the device data sheet. entry condition pta0 ?this pin must be configured as an input and pulled up in hardware. exit condition a ?contains data received from pta0. c bit usually the c bit is set, indicating proper reception of the stop bit. however, if the c bit is clear, a framing error occurred. therefore, the received byte in a is not reliable.
on-chip flash programming routines, rev. 4 8 freescale semiconductor how to use the routines example 1: receiving a byte serially example 1 shows how to receive a byte serially on pta0: getbyte equ $037e ;lb8 getbyte jump address bclr 0,ddra0 ;configure port a bit 0 as an input jsr getbyte ;call getbyte routine bcc frameerror ;if c bit is clear, framing error ; occurred. take a proper action note after getbyte is called, the program will remain in this routine until a start bit (0) is detected and a complete character is received. putbyte putbyte is a routine that receives a byte on the general-purpose i/o pta0. the sent value must be loaded into the accumulator (a) before calling this routine. this routine is also used in the monitor mode. therefore, it uses the same non-return-to-zero (nrz) communication protocol. the communication baud rates are the same as those described in getbyte. to use this routine, some hardware setup is required. the general-purpose i/o pta0 must be pulled up and configured as an input and the pta0 data bit must be initialized to 0. interrupts are not masked and the cop is not serviced in the putbyte routine. user software should ensure that interrupts are blocked during character transmission. entry condition a ?contains data sent from pta0 pta0 this pin must be configured as an input and pulled up in hardware and the pta0 data bit must be initialized to 0. exit condition a and x ?are restored with entry values.
how to use the routines on-chip flash programming routines, rev. 4 freescale semiconductor 9 example 2: sending a byte serially example 2 shows how to send a byte ($55) serially on pta0: putbyte equ $0381 ;lb8 putbyte jump address bclr 0,ddra ;configure port a bit 0 as an input bclr 0,pta ;initialize data bit to zero pta0=0 lda #$55 ;load sent data $55 to a jsr putbyte ;call putbyte routine rdvrrng when using the rdvrrng routine, the user must select one of the following function options: send-out option used to read a range of flash locations and to send the read data to a host through pta0 by using the putbyte routine. verify option ?used to read a range of flash locations and to verify the read data against the data array. send-out option if the accumulator (a) is initialized with $00 at the routine entry, the read data will be sent out serially through pta0. the communication baud rate is the same as the baud rate described in the putbyte routine. when this option is selected, the pta0 must be pulled up and configured as an input and the pta0 data bit must be initialized to 0. verify option if a is initialized with a non-zero value, the read data is verified against the data array for each byte of flash and the data array is replaced by the data read from flash. if the data does not match the corresponding value, the data read from flash can be confirmed in the data array. all data in the data array must be in the zero page, but a range can be beyond a row size or a page size. carry (c) bit and checksum the first and last addresses of the range to be read and/or verified are specified as parameters in registers h:x and laddr, respectively. in the verify option, the carry (c) bit of the condition code register (ccr) is set if the data in the specified range is verified successfully against the data in the data array. however when the send-out option is selected, the status of the c bit is meaningless because this function does not include the verify operation. both options calculate a checksum on data read in the range. this checksum, which is the lsb of the sum of all bytes in the entire data collection, is stored in a upon return from the function. interrupts are not masked. the cop is serviced in rdvrrng. the first cop is serviced at 23 bus cycles after this routine is called in the user software. however, the cop timeout might still occur in the send-out option if the cop is configured for a short timeout period.
on-chip flash programming routines, rev. 4 10 freescale semiconductor how to use the routines entry condition h:x ?contains the beginning address in a range. laddr ?contains the last address in a range. a when a contains $00, read data is sent out via pta0 (send-out option is selected). when a contains a non-zero value, read data is verified against the data array (verify option is selected). data array ?contains data to be verified against flash data. for the send-out option, the data array is not used. pta0 ?when the send-out option is selected, this pin must be configured as an input and pulled up in hardware and pta0 must be initialized to 0. exit condition a ?contains a checksum value. h:x ?contains the address of the next byte immediately after the range read. c bit ?indicates the verify result (only applies to the verify option). when the c bit is set, the verify succeeded. when the c bit is cleared, the verify failed. data array ?replaced with data read from flash when the verify option is selected. example 3: verify option example 3 shows how to use the verify option: rdvrrng equ $0384 ;lb8 rdvrrng jump address ldhx #$0000 ;index offset into data array lda #$aa ;initial data value to store in array data_load: coma sta data,x ;fill data array, 32 bytes data, ; to verify against programmed flash aix #1 ; data (in this example verifying data cphx #$20 ; is $55, $aa, $55, $aa....) bne data_load ldhx #$c01f ;load last address of range to sthx laddr ; laddr ldhx #$c000 ;load beginning address of range ; to h:x lda #$55 ;write non-zero value to a to select ; the verify option jsr rdvrrng ;call rdvrrng routine bcc error ;if bit c is cleared, verify failed ; take a proper action ; a contains a checksum value
how to use the routines on-chip flash programming routines, rev. 4 freescale semiconductor 11 example 4: send-out option example 4 shows how to use the send-out option: rdvrrng equ $0384 ;lb8 rdvrrng jump address bclr 0,ddra ;configure port a bit 0 as an input bclr 0,pta ;initialize data bit to zero pta0=0 ldhx #$c025 ;load last address of range to sthx laddr ; laddr ldhx #$c010 ;load beginning address of range ; to h:x clra ;a=0 to select send-out option jsr rdvrrng ;call rdvrrng routine ; a contains a checksum value prgrnge prgrnge is used to program a range of flash locations with data loaded into the data array. the range must be less-than or equal-to 32 bytes. all bytes that will be programmed must be in the same row. programming data is passed to prgrnge in the data array. the size of the data array must match the size of a specified programming range. this routine supports an internal operating frequency between 1.0 mhz and 8.4 mhz. for this split-gate flash, the programming algorithm requires a programming time (t prog ) between 30 s and 40 s. (refer to the flash memory section in the device data sheet.) table 4 shows how t prog is adjusted by a cpuspd value in this routine. the cpuspd value is the nearest integer of f op (in mhz) multiplied by 4. for example, if f op is 2.4576 mhz, the cpuspd value is 10 ($0a). if f op is 8.0 mhz, the cpuspd value is 32 ($20). in prgrnge, the high programming voltage time is enabled for less than 125 s when programming a single byte at any operating bus frequency between 1.0 mhz and 8.4 mhz. therefore, even when a row is programmed by 32 separate single-byte programming operations, the cumulative high voltage programming time is less than the maximum t hv (4 ms). the t hv is defined as the cumulative high voltage programming time to the same row before the next erase. for more information, refer to the memory characteristics in the electrical specifications section of the device data sheet. this routine does not confirm that all bytes in the specified range are erased prior to programming. nor does this routine perform a verification after programming, so there is no return confirmation that programming was successful. to program data successfully, the user software is responsible for these table 4. t prog vs. bus frequency operating bus freq. (f op ) cpuspd t prog (cycles) t prog case 1 1.0 mhz f bus < 1.125 mhz 4 38 33.8 s < t prog 38.0 s case 2 1.125 mhz f bus 8.4 mhz 5 to 34 8 x cpuspd + 5 32.1 s t prog 40.0 s
on-chip flash programming routines, rev. 4 12 freescale semiconductor how to use the routines verifying operations. the rdvrrng routine can be used to verify a programmed flash range against the data array. interrupts are masked and the cop is serviced in this routine. the first cop is serviced at 59 bus cycles after this routine is called in the user software. entry condition h:x ?contains the beginning address in a range. laddr ?contains the last address in a range. cpuspd ?contains the nearest integer value of f op (in mhz) times 4. data array ?contains the data values to be programmed into flash. exit condition h:x ?contains the address of the next byte after the range just programmed. example 5: programming a row example 5 shows how to program one full 32-byte row: prgrnge equ $038a ;lb8 prgrnge jump address ldhx #$0000 ;index offset into data array lda #$aa ;initial data value (inverted) data_load: coma ;alternate between $55 and $aa sta data,x ;fill data array, 32 bytes data, ; values to program into flash aix #1 ; (ie. 55, aa, 55, aa....) cphx #$20 bne data_load mov #$0a,cpuspd ;fop = 2.4576mhz in this example ldhx #$c01f ;load last address of the row sthx laddr ; to laddr ldhx #$c000 ;load beginning address of the ; row to h:x jsr prgrnge ;call prgrnge routine
how to use the routines on-chip flash programming routines, rev. 4 freescale semiconductor 13 example 6: programming a range smaller than a row prgrnge can be used to program a range less than 32 bytes. example 6 shows how to program $55 and $aa at location $e004 and $e005, respectively. prgrnge equ $038a ;lb8 prgrnge jump address mov #$55,data mov #$aa,data+1 mov #$18,cpuspd ;fop = 6.0mhz in this example ldhx #$e005 ;load last address to laddr sthx laddr ldhx #$e004 ;load beginning address to h:x jsr prgrnge ;call prgrnge routine erarnge erarnge can be called to erase a page (64 bytes) or a whole array of flash. registers h and x can be any address within the page or array to be erased. to select erase size, ctrlbyt is used. writing $40 to ctrlbyt selects the entire array (mass) erase. writing $00 to ctrlbyt selects the page erase. when other values are written to ctrlbyt, the erase operation is not executed. this routine supports an internal operating frequency between 1.0 mhz and 8.4 mhz. in this routine, both page erase time (t erase ) and mass erase time (t merase ) are set between 4 ms and 5.5 ms. the cpuspd value is the nearest integer of f op (in mhz) times 4. for example if f op is 3.1 mhz, the cpuspd is 12 ($0c). if f op is 4.9152 mhz, the cpuspd is 20 ($14). interrupts are masked and the cop is serviced in erarnge. the first cop is serviced on (40+3xcpuspd) bus cycles after this routine is called in the user software. entry condition ctrlbyt ?for mass erase, write $40. for page erase, write $00. h:x ?contains an address within a desired erase page or an array. cpuspd ?contains the nearest integer value of f op (in mhz) times 4. exit condition none
on-chip flash programming routines, rev. 4 14 freescale semiconductor how to use the routines example 7: erasing an entire array example 7 shows how to erase an entire array: erarnge equ $0387 ;lb8 erarnge jump address mov #$08,cpuspd ;fop = 2.0mhz in this example mov #$40,ctrlbyt ;select mass erase operation ldhx #$e000 ;load any flash address to h:x jsr erarnge ;call erarnge routine example 8: erasing a page example 8 shows how to erase a page from $e100 through $e13f: erarnge equ $0387 ;lb8 erarnge jump address mov #$14,cpuspd ;fop = 4.9152mhz in this example mov #$00,ctrlbyt ;select page erase operation ldhx #$e121 ;load any address within the ; page to h:x jsr erarnge ;call erarnge routine if the flash locations that you want to erase are protected due to the value in the flash block protect register (flbpr), the erase operation will not be successful. however when a high voltage (v tst ) is applied to the irq pin, the block protection is bypassed. when the flash security check fails in the normal monitor mode, the flash can be re-accessed by erasing the entire flash array. to override the flash security mechanism and erase the flash array using this routine, registers h and x must contain the address of the flash block protect register (flbpr).
how to use the routines on-chip flash programming routines, rev. 4 freescale semiconductor 15 delnus delnus is a delay routine used in support of the erarnge routine. it can, however, be called independently in the user software. delnus uses two parameters stored in the accumulator (a) and the x register (x). neither of these parameters is passed as an absolute value. the total delay (cycles) resulting from this routine is: delnus = 3 (a value) (x value) + 8 cycles where a value of a is 4 or greater and a value of x is 1 or greater. in the erarnge routines, the cpuspd value (which is a frequency parameter) is loaded into a. because this routine is called from a jump table, three additional cycles are included in the above equation. interrupts are not masked and the cop is not serviced in delnus. initialization a ?select a value between 4 and 255 x ?select x value between 1 and 255 exit condition none example 9: generating a delay initialized a = 16 and x = 8 to generate 100 s delay at f op = 4 mhz delnus equ $038d ;lb8 delnus jump address lda #$10 ;[2]a=16 ldx #$08 ;[2]x=8 jsr delnus ;[4]call delnus routine in this example, the total delay time is 8 + (3 16 8 + 8) cycles = 400 cycles (100 s).
on-chip flash programming routines, rev. 4 16 freescale semiconductor on-chip routines flowcharts on-chip routines flowcharts figure 1. getbyte routine rotate a right through c bit c c getbyte pta0 = 0 ? call getbit routine to get start bit c bit = 1 ? a = $80 call getbit routine to get data c bit = 0 ? call getbit routine to get stop bit (note 1) rts a yes no yes no yes no nextbit: notes: 1. when c bit is 0, communication has a framing error.
on-chip routines flowcharts on-chip flash programming routines, rev. 4 freescale semiconductor 17 figure 2. getbit routine ( ) getbit push x to stack push a to stack a = #offseti x = #sampperbiti ecgst bit in oscstat = 1? yes no (external clock) a = #offsete x = #sampperbite read pta0 a = a ?c when pta0 = 1, c bit = 1 when pta0 = 0, c bit = 0 decremented x = 0 yes no ? rotate a left through c bit c c a (note 1) notes: 1. if rotated a is a negative value, a bit is logic 1. pull stack data y to a pull stack data x to x rts seriale: loopin:
on-chip flash programming routines, rev. 4 18 freescale semiconductor on-chip routines flowcharts figure 3. putbyte routine putbyte save x to stack save a (transmit data) to stack a = 10 pta0 = 0 yes no ? make ~2 bit delay decrement x = 0 no yes ? x = #bitx2 c bit = 1 (stop bit) rotate transmit data (stack) c c transmit data right through c bit c bit = 0 no ? set pta0 as input (note 1) yes set pta0 as output ecgst bit in oscstat = 0? yes no (internal clock) (note 2) adjust bit timing for internal clock x = bittimei adjust bit timing for external clock x = bittimee decremented x = 0 yes no ? are 10 bits sent? (decremented a = 0) rts restore transmit data (stack) to a restore x from stack notes: 1. pta0 input pulls up high. 2. pta0 output drives low. outhi: outlow: outdelay: no yes delout:
on-chip routines flowcharts on-chip flash programming routines, rev. 4 freescale semiconductor 19 figure 4. rdvrrng routine rdvrrng calculate total byte number to be read store total byte number at result and byte counter (stack) service cop read flash data at h:x initialized a = $00? decrement result replace data array with flash read data rts yes no data array data = flash read data? accumulate checksum h:x = h:x + 1 decrement byte counter = 0? call putbyte routine to send data to host no yes no yes result = 0 ? clear c bit set c bit a = total checksum verify pass verify fail no yes readdata: nodatamatch: checksum: serial:
on-chip flash programming routines, rev. 4 20 freescale semiconductor on-chip routines flowcharts figure 5. prgrnge routine, part 1 set i bit (mask interrupts) prgrnge total byte number = 0 no yes save data at laddr and laddr+1 to stack calculate total byte number to be programmed and store the value at stack point to first byte in data array rampntrlo = $00 ? total byte number #loopcop ? total byte number = $00 total byte number = total byte number ?#loopcop bytecntr = #loopcop call prgstep1 routine rts restore original values at laddr and laddr+1 yes no progend loopprog: program: bytecntr = total byte number
on-chip routines flowcharts on-chip flash programming routines, rev. 4 freescale semiconductor 21 figure 6. prgrnge routine, part 2 service cop prgstep1 step 9: decremented no step 1: set pgm bit step 2: read flbpr bytecntr = 0? step 3: write any data to a flash address (h:x) step 4: delay t nvs step 5: set hven bit step 6: delay t pgs read ram data pointed step 7: write data to a step 8: delay t prog [bus cycles] for cpuspd = 4, prgstep7: by rampntrlo flash address (h:x) for cpuspd = 5 to 34, t prog = 2 x cpuspd ?9 t prog = 38 h:x = h:x + 1 set a next ram location by incrementing rampntrlo yes step 10: clear pgm bit step 11: delay t nvh step 12: clear hven bit service cop rts
on-chip flash programming routines, rev. 4 22 freescale semiconductor on-chip routines flowcharts figure 7. erarnge routine step 7: clear erase bit step 8: delay t nvhl step 9: clear all bits in flcr call delnus routine (note 1) decremented loop erarnge rts set i bit mass bit sets in yes step 2: read flbpr step 3: write any data to step 4: delay t nvs flash address (h:x) step 5: set hven bit step 6: set loop counter = 20 service cop (mask interrupts) ctrlbyt? no step 1: set erase and mass bits step 1: set erase bit mass erase page erase counter = 0? no yes step 10: delay t rcv servicecop: to make ~200- s delay ctrlbyt = $00 or $40 yes ? no 1. delnus routine is used note s:
on-chip routines flowcharts on-chip flash programming routines, rev. 4 freescale semiconductor 23 figure 8. delnus routine push a value to stack pull a value from stack (2 cycles) decremented rts yes no delnus decrement a (1 cycle) (2 cycles) decrement a (1 cycle) decremented a value = 0? (3 cycles) x value = 0? (3 cycles) (4 cycles) no yes loop: decrement a (1 cycle)
on-chip flash programming routines, rev. 4 24 freescale semiconductor on-chip routines source code on-chip routines source code the following source code is for the mc68hc908lb8 on-chip routines. because other mcus support different communication baud rates, getbit and putbyte routines are slightly different. however, these routines are built in the same manner. .pagewidth 98t ;********************************************************************** ;* purpose: this program has the hc908lb8 flash program, erase, verify ;* routines and serial communication routines. ;* ;* target device: hc908lb8 ;* ;* assembler: p&e microsystems casm08z ;* version: 3.16 ;* ;* general coding notes: ;* a standard equate file "908lb86vxry.inc" is used to define all mcu ;* register and bit names. bit names use all uppercase characters. ;* bclr, bset, brclr, and brset use the bit name alone while logical ;* instructions such as ora use the bit name with a prefix of ;* lowercase "m" which is a bit position mask. ;********************************************************************* ;********************************************************************* ;* assembler directives ;* (base, macros, sets, conditions, etc.) ;********************************************************************* base 10t ;change default to decimal ;********************************************************************* ;* included files ;********************************************************************* $nolist include "908lb8v0r2.inc" $list ;********************************************************************* ;* equates for rom assigned locations ;********************************************************************* ;* rom assigned location ;* jumptable: equ $037e ;jump table start address flashrom: equ jumptable+$1b ;flash rom start address ;********************************************************************* ;* equates and variables for getbit and putbyte routines ;* constants used in the getbit and putbyte routines: ;* note: changing the following parameters will alter the baud rate! ;* external clock (ext) values set for 9600 baud @ 2.4576mhz bus rate ;* internal clock (int) values set for 9600 baud @ 4.0mhz bus rate ;********************************************************************* sampperbite: equ 22 ;samples per bit time (ext) sampperbiti: equ 38 ;(int) used in getbit offsete: equ 15 ;~70% sampperbit (ext) and (int) offseti: equ 27 ; used in getbit
on-chip routines source code on-chip flash programming routines, rev. 4 freescale semiconductor 25 ;* more than offset samples = 1 means bit is detected as a logic 1 bitx2: equ 210 ;delay count for ~2 bit times ;* 2 bit time is not accurate bittimee: equ 76 ;delay count for 1 bit time (ext) and bittimei: equ 129 ; (int) used in putbyte brktimee: equ 232 ;delay count for 10 bit times (ext) brktimei: equ 123 ; and (int) used in echobrk ;********************************************************************* ;* equates and variables for flash routines ;********************************************************************* datstrc: equ ramstart+8 ;leave 8-byte offset from start of ; ram for future requirement massbit: equ 6 ;mass bit of ctrlbyt located in bit 6 rowsize: equ 32 ;flash row size org datstrc ;* the following variables set by user ctrlbyt: rmb 1 ;control byte for erase operation ; selection cpuspd: rmb 1 ;cpu bus speed (nearest integer of ; bus freq (in mhz) * 4) laddr: rmb 2 ;last address data: rmb rowsize ;allocation/use of this space depends ; on a device rampntrlo: equ laddr ;laddr loc. reused as ram pointer in ; prgrnge routine bytecntr: equ laddr+1 ;laddr+1 loc. reused as byte count in ; prgrnge routine ;* these times are for use by erarnge looperase: equ 20 ;total terase time (~ 4ms) ; =20+(eraseloop*(3*cpuspd*terase+26)) terase: equ 17 ;flash erase time between cop service ; cop is serviced every ~200 us = ; 3*cpuspd*terase+26 (bus cycles) tnvhl: equ 9 ;flash high-voltage hold time (>= 100us) ; = 3*spuspd*tnvhl+19 (bus cycles) loopcop: equ 6 ;cop is serviced when loopcop reaches ; to zero ;********************************************************************* ;* jump table ;********************************************************************* org jumptable byteget: jmp getbyte ;receive one byte data from a host byteput: jmp putbyte ;send one byte data to a host rngrdvr: jmp rdvrrng ;read/verify flash data rngeera: jmp erarnge ;erase flash rngeprg: jmp prgrnge ;program flash nusdel: jmp delnus ;generate delay ********************************************************************** * routines ********************************************************************** org flashrom
on-chip flash programming routines, rev. 4 26 freescale semiconductor on-chip routines source code ;********************************************************************* ;* name: getbyte ;* purpose: ;* get one byte data through pta0 serially. this routine supports ;* a baud rate 9600 bps at internal 4mhz and external 2.4576mhz bus ;* frequencies. a clock is distinguished by the state of ecgst bit ;* (bit 0) in oscstat. when ecgst=1, an external clock is selected. ;* entry conditions: ;* pta0 configured as an input. ;* exit conditions: ;* a contains a byte received when start bit is detected ;* c-bit in ccr indicates a framing error ;* if c-bit is cleared, a framing error is indicated because ;* the stop bit was detected as a 0 instead of a 1 ;* pta0 configured as an input ;* subroutines called: getbit ;* variables read: ;* variables modified: ;* stack used: 6 (including the call to this routine) ;* size: 18 bytes ;* description: executed out of rom ;* once called, program will remain in getbyte until a byte is ;* received. signal to start receiving a byte is a valid ;* (low) start bit. ;* this routine does not service cop. ;* note: cycle path for each bit reception must be kept the same to ;* maintain a steady baud rate. ;* when oscstat[0]=0 (internal clock is selected): ;* 9+(28+10*38)= 417 cycles @ 4.0 mhz=104.3 us=9592 bps ;* (closest pc baud rate 9,600 bps) ;* when oscstat[0]=1 (external clock is selected): ;* 9+(27+10*22) = 256 cycles @ 2.4576 mhz = 104 us = 9,600 bps ;********************************************************************* getbyte: brset 0,pta,getbyte ;[.r...] loop till pta0=0 (start) bsr getbit ;[4+getbit] check sense of start bit bcs getbyte ;[3] c-bit should be 0, else noise lda #$80 ;[2] rx byte done when 1 rors into c nextbit: ; top of loop to get 8 bits bsr getbit ;[4+getbit] sense level of next bit rora ;[1] rotate into a from left nop ;[1] pad to tune timing bcc nextbit ;[3] continue 'till 1 rors into c stpbit: bsr getbit ;[4+getbit] sense level of stop bit rts ;[4] ;* getbyte done ****************** ;********************************************************************* ;* name: putbyte ;* purpose: ;* send one byte data through pta0 serially. this routine supports ;* a baud rate 9600 bps at internal 4mhz and external 2.4576mhz bus ;* frequencies. a clock is distinguished by the state of ecgst bit ;* (bit 0) in oscstat. when ecgst=1, an external clock is selected. ;* entry conditions: ;* pta0 configured as an input, pta0 data bit = 0 ;* a contains data to be sent ;* exit conditions:
on-chip routines source code on-chip flash programming routines, rev. 4 freescale semiconductor 27 ;* a and x is restored to entry values ;* pta0 configured as an input (pta0=high idle line) ;* subroutines called: ;* variables read: ;* variables modified: ;* stack used: 4 (including the call to this routine) ;* size: 46 bytes ;* description: executed out of rom ;* after ~2 bit times delay, a character in a is sent via pta0 ;* once called, program will remain in putbyte until pta0=high ;* this routine does not service cop ;********************************************************************* putbyte: pshx ;[2] save x psha ;[2] temp save tx data lda #10 ;[2] start, 8 data, stop = 10 loops brclr 0,pta,* ;[.r...] wait for pta0 high (idle) ldx #bitx2 ;[2] load constant for ext ;* delay ~2 bit times before transmitting data (time not critical) ;* ext 2 bit is 25% longer and int 2 bit is 23% shorter delay: dbnzx delay ;[3] loop 3 cyc * bitx2i sec ;[1] becomes stop bit after 9 rors bra outlow ;[3] tx a low for start bit putloop: ror 1,sp ;[5] lsb to c-bit, tx that level bcc outlow ;[3] if c=0 tx low, else tx high outhi: bclr 0,ddra ;[4] pta0 input pulls up to high bra outdelay ;[3] go to time 1 bit delay outlow: bset 0,ddra ;[4] pta0 output makes pin drive low bra outdelay ;[3] time 1 bit delay (match time) outdelay: ldx oscstat ;[3] check for int/ext clk bne bite ;[3] branch if ext (oscstat!=$00) ldx #bittimei ;[2] load int bit delay bra delout ;[3] skip to delout bite: nop ;[1] timing adjust ldx #bittimee ;[2] load ext bit delay delout: dbnzx delout ;[3] loop 3~ * (value in x) nop ;[1] timing adjust dbnza putloop ;[3] repeat for start, 8 data, stop pula ;[2] restore tx data pulx ;[2] restore x rts ;[4] ;* putbyte done ****************** ;********************************************************************* ;* name: getbit ;* purpose: ;* receive one serial bit via pta0 and return it in c-bit ;* entry conditions: ;* pta0 configured as an input. ;* exit conditions: ;* a and x is restored to entry values ;* bit level is returned to c bit in ccr ;* pta0 configured as an input. ;* subroutines called: getbit ;* variables read:
on-chip flash programming routines, rev. 4 28 freescale semiconductor on-chip routines source code ;* variables modified: ;* stack used: 4 (including the call to this routine) ;* size: 31 bytes ;* description: executed out of rom ;* execution cycle for internal and external is: ;* internal (oscstat[0]=0) = 28 + (10 x sampperbiti) ;* extnernal (oscstat[0]=1) = 27 + (10 x sampperbite) ;********************************************************************* getbit: pshx ;[2] preserve x psha ;[2] preserve a nop ;[1] time padding brset 0,oscstat,seriale ;[5] check if int or ext clk lda #offseti ;[2] # of samples to detect 1 (int) ldx #sampperbiti ;[2] # of samples per bit (int) brclr 0,oscstat,loopin ;[5] time matching padding seriale: lda #offsete ;[2] # of samples to detect 1 (ext) ldx #sampperbite ;[2] # of samples per bit (ext) nop ;[1] time padding bra loopin ;[3] time padding loopin: brclr 0,pta,subsamp ;[5] set/clr c based on pta0 level subsamp: sbc #0 ;[2] subtract c from offset in a dbnzx loopin ;[3] loop sampperbiti times rola ;[1] copy msb to c bit (1 if a neg) ;* a would be negative if # of 1 samples was > offsetg_ ;* c bit reflects detected sense of current serial bit pula ;[2] restore a pulx ;[2] restore x rts ;[4] return ;* getbit done ****************** ;********************************************************************* ;* name: rdvrrng ;* purpose: read and/or verify a range of flash memory ;* entry conditions: ;* h:x contains a start address of the flash address range ;* laddr:laddr+1 contains a last address of the flash address range ;* the contents of a decides if read data is transferred serially ;* via pta0 (when a=0, pta0 is used for serial transfer) or ;* the data is verified against the data array in ram ;* data array contains the data to be verified ;* if a=0, pta0 is configured as an input (ddra0=0) and ;* data bit = 0 (pta0=0) ;* exit conditions: ;* a contains checksum ;* c-bit in ccr indicates verify result when entry a is not zero ;* if c-bit is set, the verify is successful ;* data array contains read flash data when entry a is not zero ;* h:x contains a next flash read address ;* subroutines called: putbyte ;* variables read: laddr:laddr+1,data array ;* variables modified: data array ;* stack used: (include the call to this routine) ;* 9 bytes for verify operation (entry a is not zero) ;* 11 bytes for data send out operation (entry a is zero) ;* size: 67 bytes ;* description: executed out of rom ;* the cop is serviced in this routine. the first cop is serviced on
on-chip routines source code on-chip flash programming routines, rev. 4 freescale semiconductor 29 ;* 23 bus cycles after this routine is called in the user software. ;* however, the cop timeout might still occur under the following ;* conditions: ;* 1) cop is not serviced within a proper period in user software ;* 2) cop set for short timeout and read data is sent through pta0 ;* stack frame: ;* sp+1 [g] saddr(hi) temp storage ;* sp+2 [f] saddr(lo) temp storage ;* sp+3 sp+1 [e] bytecount - decrements to zero ;* sp+4 sp+2 [d] # of bad bytes - 0 on return means all were good ;* sp+5 sp+3 [c] checksum - sum of all data values read ;* sp+6 sp+4 [b] offset pointer into data array in ram ;* sp+7 sp+5 [a] verify/read flag - 1=verify/0=read ;* | | | ;* | | +--reference label in square brackets ;* | +---sp offset when saddr not on stack ;* +---------sp offset when saddr on stack for temp storage ;********************************************************************* rdvrrng: psha ;verify(1)/read(0) flag to stack [a] clra psha ;offset pointer into data array in ; ram [b] (initially 0) ; increments from $00 to bytecount psha ;initial checksum to stack [c] ;calculate total # of bytes txa ;saddr(lo) -> a sub laddr+1 ;saddr(lo) - laddr(lo) -> a nega ;laddr(lo) - saddr(lo) -> a inca ;change to 1-oriented vs 0-oriented psha ;# of bytes to stack [d] (# of bad) ; decrements to zero if all good psha ;bytecount to stack [e] ; counter - decrements to zero readdata: sta copctl ;service cop lda ,x ;data from a flash location @ 0,x tst 5,sp ;check read/verify flag [a] beq serial ;0 - send data through pta0 ;1 - verify against data in ram pshx ;push saddr(lo) to stack [f] pshh ;push saddr(hi) to stack [g] ldx 6,sp ;data array pointer(lo) -> x clrh ;h:x = 0:pointer(lo) cmp data,x ;compare flash data with data array bne nodatamatch ;if not equal, skip decrement of [d] dec 4,sp ;data matched so decrement # of bad nodatamatch: sta data,x ;replace data array value with ; value read from flash pulh ;restore saddr(hi) pointer from [g] pulx ;now h:x = saddr, a is flash data bra checksum ;skip serial send if in verify mode serial: jsr putbyte ;read mode so send data to host checksum: add 3,sp ;flash data + checksum [c] -> a sta 3,sp ;update checksum [c] on stack inc 4,sp ;update offset into data array [b]
on-chip flash programming routines, rev. 4 30 freescale semiconductor on-chip routines source code aix #1 ;update pointer into flash (h:x) dec 1,sp ;decrement bytecount [e] bne readdata ;loop until bytecount=0 pula ;deallocate [e] pula ;# of bad [d] -> a, and deallocate ;if verify ok, a = $00 coma ;$00 -> $ff if verify ok add #1 ;$ff -> $00; c=1 if verify was ok pula ;checksum [c] -> a, and deallocate ais #2 ;deallocate [a] and [b] rts ;* rdvrrng done ****************** ;********************************************************************* ;* name: prgrnge ;* purpose: ;* program a flash address range which is maximum 32 bytes in the ;* same row. bus frequency must be between 1.0mhz and 8.4mhz. ;* entry conditions: ;* h:x contains a start address of the flash address range ;* laddr:laddr+1 contains a last address of the flash address range ;* data array contains the data to be programmed to the flash ;* (maximum 32 bytes) ;* cpuspd contains a nearest integer of 4 x bus frequency (mhz) ;* exit conditions: ;* h:x contains a next flash address; i-bit set ;* subroutines called: ;* variables read: cpuspd, laddr:laddr+1, data array ;* variables modified: laddr(bytecntr):laddr+1(rampntrlo) ;* the values are modified, but they are restored with original ;* values before exiting from this routine. ;* stack size: 9 bytes (including the call to this routine) ;* size: 132 bytes ;* description: executed out of rom ;* this routine can program the flash only in the same row. ;* therefore, the total programing byte no. is maximum 32 bytes. ;* the cop is serviced in this routine. the first cop is serviced on ;* 59 bus cycles after this routine is called in the user software. ;* however, there could still be a cop time out if the cop is not ;* serviced within a proper period in user software. ;********************************************************************* prgrnge: sei ;set i bit to mask interrupts lda laddr psha ;save laddr(hi) to stack [a] lda laddr+1 psha ;save laddr(lo) to stack [b] pshx ;calculate total # of bytes ; to be programmed pula ;sladdr (lo) -> a sub laddr+1 ;saddr(lo) - laddr(lo) -> a nega ;laddr(lo) - saddr(lo) -> a inca ;change to 1-oriented vs 0-oriented psha ;[c] total remaining bytes to prog ; will decrement by loopcop on each ; pass through loopprog startprog:
on-chip routines source code on-chip flash programming routines, rev. 4 freescale semiconductor 31 clr rampntrlo ;start with 1st loc. in data array ;* current stack frame ;* sp+2 [c] total bytes left to program; count down to zero ;* sp+3 [b] laddr(lo) used to restore last addr before rts ;* sp+4 [a] laddr(hi) ;********************************************************************* ;* cop is serviced before each block of loopcop bytes are programmed ;* loopprog is the top of the outer loop. bsr prgstep1 programs up to ;* loopcop bytes before return (last batch may be fewer than loopcop) loopprog: lda 1,sp ;[c] total bytes remaining to prog beq progend ;if zero, programing is done cmp #loopcop ;bytes remaining >= loopcop ? bge initprog ;if so, skip to initprog sta bytecntr ;< so make bytecntr = bytesremaining clr 1,sp ;and clear bytesremaining at [c] bra program ;go program last partial block initprog: sub #loopcop ;>= so subtract loopcop sta 1,sp ;bytes remaining reduced by loopcop lda #loopcop ;prepare to prog loopcop bytes sta bytecntr ;bytecntr = loopcop program: bsr prgstep1 ;program up to loopcop bytes bra loopprog ;repeat outer loop...check number of ;bytes remaining progend: pula ;deallocate [c] pula sta laddr+1 ;restore an original value to laddr+1 pula sta laddr ;restore an original value to laddr rts ;********************************************************************* ;* flash programming algorithm ;********************************************************************* prgstep1: sta copctl ;[4] service cop ;before programming bytecntr bytes lda #mpgm ;[2] sta flcr ;[..w.] set pgm (prog algo step 1) prgstep2: lda flbpr ;[4] read flbpr (prog algo step 2) prgstep3: sta ,x ;[2] write to flash address [h:x] ; w/ any data (prog algo step 3) prgstep4: lda cpuspd ;[3] delay for time tnvs dbnza * ;[3*cpuspd] (prog algo step 4) prgstep5: lda #(mpgm+mhven) ;sets hven and leaves pgm set sta flcr ;[..w.] set hven (prog algo step 5) prgstep6: lda cpuspd ;[3] delay for time tpgs dbnza * ;[3*cpuspd] (prog algo step 6)
on-chip flash programming routines, rev. 4 32 freescale semiconductor on-chip routines source code ;********************************************************************* ;* step 7 and step 8 are repeated until a value in location laddr+1 ;* reaches to zero. ;********************************************************************* prgstep7: pshx ;[2] temp flash pointer (lo) [f] pshh ;[2] temp flash pointer (hi) [g] ;* current stack frame ;* sp+1 [g] flash pointer (hi) temp store so h:x available ;* sp+2 [f] flash pointer (lo) temp store so h:x available ;* sp+3 [e] pch (return addr hi) ;* sp+4 [d] pcl (return addr lo) ;* sp+5 [c] bytes remaining to prog..not counting this block ;* sp+6 [b] laddr+1 ;* sp+7 [a] laddr clrh ;[1] clear upper half of h:x ldx rampntrlo ;[3] get data array pointer (lo) lda data,x ;[3] read data from a data array pulh ;[2] restore flash pointer (hi) [g] pulx ;[2] restore flash pointer (lo) [f] sta ,x ;[.w] write data to flash addr ; (prog algo step 7) ;********************************************************************* ;* compute tprog based on bus speed ;* for slowest bus speeds (cpuspd=4), tprog = 38 bus cycles. for ;* other speeds, tprog = 8 * cpuspd + 5 bus cycles. prgstep8: ;delay for tprog (prog algo step 8) lda cpuspd ;[3] cmp #4 ;[2] if cpuspd=4 (bus = 1mhz), beq prgstep9 ;[3] tprog=38 cycles asla ;[1] for other cases sub #9 ;[2] a = 2 x cpuspd - 9 delayprg: nop ;[1] 1~ delay dbnza delayprg ;[3] tprog = 8 * cpuspd + 5 cycles prgstep9: ; (prog algo step 9) aix #1 ;[2] point to next flash address inc rampntrlo ;[4] increment data array pointer dec bytecntr ;[4] decrement byte counter bne prgstep7 ;[3] loop until byte counter is = 0 rol 1,sp ;[5] rol/ror/sei makes 12~ delay ror 1,sp ;[5] to match delay to prgstep10 sei ;[2] prgstep10: lda #mhven ;[2] clear pgm, leave hven=1 sta flcr ;[..w.] (prog algo step 10) prgstep11: lda cpuspd ;[3] delay for time tnvh dbnza * ;[3*cpuspd] (prog algo step 11) prgstep12: clra ;[1] pattern to clear hven sta flcr ;[..w.] clear hven bit in flcr
on-chip routines source code on-chip flash programming routines, rev. 4 freescale semiconductor 33 ;clr hven (prog algo step 12) sta copctl ;[4] service cop rts ;[4] ;* prgrnge done ****************** ;********************************************************************* ;* name: delnus ;* purpose: generate delay (3 * a * x) + 5 [cycles] ;* entry conditions: ;* a contains an integer value equal to 4 or higher ;* x contains an integer value equal to 1 or higher ;* stack used: 3 bytes (including the call to this routine) ;* size: 10 bytes ;* description: executed out of rom ;* this routine is called from erarnge routines. ;* for example when bus frequency = 4mhz, a=16, and x=17, the ;* delay time is: ;* delay time = (3 x 16 x 17) + 5 = 821 cycles (205.25us) ;* remember to consider delays associated with setup and jsr/bsr ;********************************************************************* delnus: deca ;[1] a - 1 loop: psha ;[2] temp save deca ;[1] original a - 2 deca ;[1] original a - 3 dbnza * ;[3(orig a - 3)] (inner loop) pula ;[2] recover original a - 1 dbnzx loop ;[3] (bottom of outer loop) ;* outer loop = (x(2+1+1+(3(a-3))+2+3)) = (x(9+(3a-9)) = 3 * x * a rts ;[4] ;* delnus done ****************** ;********************************************************************* ;* name: erarnge ;* purpose: ;* erase a page or a whole array in flash memory. a bus frequency ;* range has to be between 1.0mhz and 8.4mhz. ;* entry conditions: ;* h:x contains an flash address within a page or an array to be ;* erased ;* ctrlbyt selects mass erase ($40) or page erase ($00) ;* if other value is written to ctrlbyt, the erase operation ;* will not be performed ;* cpuspd contains a nearest integer of 4 x bus frequency ;* exit conditions: ;* the contents of h:x (address passed) is preserved; i-bit set ;* subroutines called: delnus ;* variables read: ctrlbyt, cpuspd ;* variables modified: ;* stack used: 7 (including the call to this routine) ;* size: 76 bytes ;* description: executed out of rom ;* does not check for a blank range before (to see if erase is ;* necessary) or after (to see if successful erase). the cop is ;* serviced in this routine. the first cop is serviced on ;* (40+3xcpuspd) bus cycles after this routine is called in the user ;* software. however, there could still be cop time out if the cop
on-chip flash programming routines, rev. 4 34 freescale semiconductor on-chip routines source code ;* is not served within a proper period in the user software. ;********************************************************************* erarnge: lda ctrlbyt ;if ctrlbyt is not either $40 or and #$bf ; $00, the operation is skipped bne finish sei ;block interrupts during erase pshx ;temp save addr(lo) to free up x erastep1: lda #merase brclr massbit,ctrlbyt,pageerase ;if massbit is set in the ctrlbyt, ora #mmass ; sets mass and erase bits in a pageerase: sta flcr ;[..w.] (erase algo step 1) ; set erase only, or mass and erase erastep2: lda flbpr ;[4] (erase algo step 2) erastep3: sta ,x ;[.w] (erase algo step 3) ;latch addr for flash page or block erastep4: lda cpuspd ;[3] delay tnvs (erase algo step 4) dbnza * ;[3+(3*a)] erastep5: lda flcr ;[4] leave mass and erase as is ora #mhven ;[2] set hven sta flcr ;[..w.] (erase algo step 5) erastep6: ;delay terase (erase algo step 6) ;slit up to allow cop service lda #looperase ;[2] initialize loop counter psha ;[2] loop count on stack for calcs ; using ' dec 1,sp' instruction servicecop: sta copctl ;[4] service cop ldx #terase ;[2] about 200us delay lda cpuspd ;[3] bsr delnus ;[4+(3*a*x)+5)] dec 1,sp ;[5] decrement loop counter bne servicecop ;[3] loop if loop count not zero ;* bottom of cop service loop ;* total terase time = setup from hven=1 + loop + overhead to erase=0 ;* = 5 + (eloops(3*a*x + 26)) + 15 33,180~ @8mhz (terase=4.148ms) pula ;[2] deallocate loop counter ; (erase algo step 7) sta copctl ;[4] service cop erastep7: lda flcr ;[4] and #{$ff-(merase+mmass)} ;[2] clear erase and mass bits sta flcr ;[..w.] (erase algo step 8) ;[2] erastep8: ldx #tnvhl ;delay for time tnvhl lda cpuspd ;[3] tnvhl is used for both bsr delnus ; page and mass erase ;[4+(3*a*x)+5)] page and mass erase
notes on-chip flash programming routines, rev. 4 freescale semiconductor 35 erastep9: ; (erase algo step 9) clra ;[1] clear all bits in flcr sta flcr ;[..w.] next 3 instructions ; including last cycle of this ; instruction make at least 1us ; delay for trcv erastep10: ; (erase algo step 10) pulx ;[2] recover original addr(lo) nsa ;[3] 3~ delay finish: rts ;[4] return from erarnge ;* erarnge done ****************** notes
AN2635 rev. 4, 10/2005 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/paci?: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters that may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals? must be validated for each customer application by customers technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2005. all rights reserved.

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